This invention pertains to three dimensional integrated circuits and methods, and systems for fabricating three-dimensional integrated circuits; more specifically this invention relates to methods and systems for interconnect metallization of three-dimensional integrated circuits.
A three-dimensional integrated circuit includes two or more semiconductor chips with integrated circuits or includes two or more semiconductor wafers with integrated circuits. The semiconductor chips or semiconductor wafers are stacked together, bonded, and electrically interconnected in three dimensions, i.e., integrated within the semiconductor chips or semiconductor wafers and integrated between the semiconductor chips or semiconductor wafers. The interconnections between the chips or between the wafers are accomplished by way of through holes from the back side to the front side of one or more of the chips or one or more of the semiconductor wafers. In other words, the electrical connections between the stack of chips or stack of wafers are made by way of the through holes. Three-dimensional integrated circuits may have a large number of through holes for interconnect metallization between the semiconductor chips or between the semiconductor wafers.
Three-dimensional integrated circuits, according to some designs, will use through-hole vias that are large, high aspect ratio features with dimensions an order of magnitude or more larger than the minimum geometry features for standard technology dual damascene metallization interconnects. Standard technology electroplating chemistry for metallization of semiconductor devices deposits a layer of metal to fill holes, trenches, and other features for gapfill. In addition to providing gapfill, overburden metal is also deposited. The overburden metal includes the portion of the metal that is deposited outside of the holes, the trenches, and the other features that are being filled. For through-hole vias, the overburden metal is the portion of the layer of metal that is deposited outside of the holes for the through hole vias. The overburden that forms in conjunction with through-hole via gapfill is thicker than that which usually occurs for two dimensional integrated circuit metallization because of the larger dimensions of the features filled for through-hole vias.
Of course, the chemical mechanical planarization process that usually follows metal gapfill is used to remove overburden metal and can be used to remove the overburden that occurs during gapfill for through hole vias for three-dimensional integrated circuits. However, chemical mechanical planarization is a slow, expensive process that may be impractical for some of the requirements of fabricating three-dimensional integrated circuits. The cost effective production of three dimensional integrated circuits will probably be more achievable if the excessive overburden metal can be removed or minimized.
Practical and cost effective fabrication of three-dimensional integrated circuits will require new processes and systems capable of meeting the requirements for metallization of three-dimensional integrated circuits. More specifically, there is a need for new processes and systems capable of meeting the unusual aspect ratio requirements for gapfill metal deposition for through hole vias in three-dimensional integrated circuits while avoiding or better accommodating the excessive overburden metal associated with the through hole via gapfill.